Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CODs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current, or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
FIG. 1a illustrates a conventional semiconductor device 10 with semiconductor die or wafer 12 in a fan-in or fan-out wafer level chip scale package (WLCSP). Semiconductor die 12 has an active surface 14 and contact pads 16 formed on the active surface. An insulating or passivation layer 18 is formed at the wafer level over active surface 14 and contact pads 16. A portion of insulating layer 18 is removed by an etching process to expose contact pads 16. An insulating or passivation layer 20 is formed at the wafer level over insulating layer 18 and the exposed contact pads 16. A portion of insulating layer 20 is removed by an etching process to expose contact pads 16. The opening in insulating layer 18 is typically 20 micrometers (μm) in order to have good contact characteristics to contact pads 16. An electrically conductive layer 22 is formed over the exposed contact pads 16 and insulating layer 20. Conductive layer 22 operates as a redistribution layer (RDL) electrically connected to contact pads 16. Conductive layer 22 extends beyond the opening in insulating layer 20 to laterally redistribute the electrical interconnect to contact pad 16. An insulating or passivation layer 24 is formed over insulating layer 20 and conductive layer 22. A portion of insulating layer 24 is removed by an etching process to expose conductive layer 22 for electrical interconnect.
FIG. 1b shows a plan view of semiconductor device 10, taken along line 1b-1b of FIG. 1a with focus on contact pad area 26. The width of opening 28 in insulating layer 20 to expose contact pad 16 for deposition of conductive layer 22 and, accordingly, the width W16-22 of the contact surface area between conductive layer 22 and contact pad 16 is 20 μm. The width between adjacent conductive layers 22 is 10 μm. An opening width W16-22 of 20 μm is necessary for good electrical characteristics between conductive layer 22 and contact pads 16. However, due to the overlap of insulating layer 20 over contact pad 16 completely around the contact pad, a certain width and pitch of contact pad 16 is required to maintain the interconnect surface area between conductive layer 22 and contact pad 16. In one embodiment, a width of contact pads 16 is 45 μm, and the contact pad pitch is 50 μm. For a 10 μm overlap of insulating layer 20 over conductive layer 16 around opening 28, the width W20-20 is 20+10+10=40 μm. The contact pad pitch of 50 μm becomes a process limitation due to the width W20-20 (width of opening 28 plus overlap width) needed for good contact characteristics. If the width W16-22 of opening 28 is reduced further, then the contact characteristics between conductive layer 22 and contact pad 16 are diminished.